module frequency_51200Hz(
	input clk_50M,
	input rst_n,
	output reg clk_51200Hz  // 50M / 51.2K = 976; count = 976 / 2 - 1 = 487
);

	reg[8:0] count;

	always @(posedge clk_50M or negedge rst_n) begin
		if(rst_n == 1'b0) begin
			count = 9'd0;
			clk_51200Hz = 1'b0;
		end
		else begin
			if(count == 9'd487) begin
				count = 9'd0;
				clk_51200Hz = ~clk_51200Hz;
			end
			else begin
				count = count + 9'd1;
			end
		end
	end

endmodule
